1. Field of the Invention
The invention relates to a MOS inverter circuit with a first load MOS FET of the depletion type, a control MOS FET of the enhancement type, a first supply voltage and a second higher supply voltage.
As is well known, MOS inverter circuits are formed of a series circuit of a control MOS FET and a load MOS FET. For example, IBM Technical Disclosure Bulletin, Vol. 22, No. 11, April 1980, describes an inverter circuit in which the control MOS FET is of the enhancement type and the load MOS FET is of the depletion type. Such a logic circuit in N-channel silicon gate technology typically operates with a supply voltage of 5 Volt, i.e., all of the conducting control MOS FETs load the voltage source with the current flowing through the load MOS FET. In many cases, however, it is necessary to use a second, higher supply voltage of, say, 20 Volt, which can frequently have a very small current drain. An application which has been used for the higher supply voltages is for E.sup.2 PROMs, in which the higher supplemental voltage is obtained from a 5-Volt voltage source, such as a low-capacity voltage mutliplier circuit. Conventional MOS inverter circuits represent an undesirable, large current drain, especially for this type of voltage source.
It is accordingly an object of the invention to provide an MOS inverter circuit, which overcomes the hereinafore-mentioned disadvantages of the hertofore-known devices of this general type, and through which the current drain from the voltage source of the higher supply voltage is reduced.